1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory device. More particularly, embodiments of the invention relate to a semiconductor memory device having a word line strap structure.
2. Discussion of Related Art
A typical semiconductor memory device having a word line strap structure comprises a main word line made of metal which crosses over a memory cell array region. A word line made of poly crosses a sub-memory cell array unit of the memory cell array and overlaps the main word line. The main word line is connected to the word line of the memory cell array.
Certain semiconductor memory devices include a word line strap structure which provides the advantage of reducing load of the word line. However, word line strap structures are rarely utilized in memory devices because it's difficult, if not impossible to reduce the width of the metal line by using conventional metal processing technology. In addition, efficiency rates for reducing the layout area size are relatively low. In view of recent developments related to metal processing technology, it may be possible to reduce the width of the metal line, thereby allowing for the use of a word line strap structure in memory devices.
FIG. 1 shows an arrangement of a memory cell array of a conventional semiconductor memory device employing a word line strap structure. The memory cell array comprises sub-memory cell arrays SMCA, sense amplifying portions SA, contact portions CT, and conjunction portions CJ. Sub-memory cell array SMCA and sense amplifying portion SA are alternately arranged in a bit line BL direction. Sub-memory cell array SMCA and the contact portion CT are alternately arranged in a word line WL direction. Sense amplifying portion SA and conjunction portion CJ are alternately arranged in a word line WL direction. The word line WL and bit line BL are arranged on a lower layer of each of the sub-memory cell arrays SMCA. Memory cells (not shown) of the array are arranged between the word line WL and the bit line BL. A main word line NWL is made of metal and arranged on an upper layer of each of the sub-memory cell arrays SMCA in a word line WL direction to overlap word line WL. The main word line NWL and the corresponding word line WL of each of the sub-memory cell arrays SMCA are connected to each other.
FIG. 2 shows a portion of the memory cell array arrangement of FIG. 1 where the word line is arranged on the lower layer of the sub-memory cell array SMCA, and the main word line is arranged on the upper layer of the sub-memory cell array SMCA to overlap the word line. On a lower layer of the sense amplifying portion SA (not shown), a PMOS sense amplifier, an NMOS sense amplifier, a column selecting gate, and a pre-charge circuit are arranged. A lower layer of the conjunction portion CJ includes a driver for driving the PMOS sense amplifier, a driver for driving the NMOS sense amplifier, and a control circuit. A contact CON connects the main word line NWL and the corresponding word line WL of the sub-memory cell arrays SMCA are arranged at a central portion of contact portion CT. That is, only contact CON is arranged on contact portion CT.
In view of advances in metal processing technology, it's possible to reduce the width E of the metal line disposed on the upper layer. However, it is difficult to reduce the length C of conjunction portion CJ because the PMOS sense amplifier driver circuit, the NMOS sense amplifier driver circuit and the control circuit are all arranged in the conjunction portion CJ having the same width D as the width of the region where sense amplifying portion SA is arranged. Thus, the efficiency for reducing the layout area size of the memory cell array is relatively low. In order to reduce the length of this region, a method for alternately arranging the PMOS transistor driver and the NMOS sense amplifier driver which comprise a large transistor in the conjunction portion CJ disposed between the sense amplifying portion SA may be considered. However, a drawback with this method is that the driving ability of the PMOS transistor driver and the NMOS transistor driver deteriorate. This occurs because all of the PMOS sense amplifiers and the NMOS sense amplifiers arranged in the sense amplifying portion SA are driven by the PMOS sense amplifier driver and the NMOS sense amplifier driver which are arranged on the upper and lower layers of the memory array.